(1) Field of the Invention
The invention generally relates to a method and apparatus used in semiconductor manufacturing and, more particularly, to a method and device for determining the reliability and predicting the end-of-life of semiconductor devices in the fabrication of integrated circuits.
(2) Description of Prior Art
Currently, various specialized test structures are used to monitor reliability wear-out mechanisms in integrated circuits. These mechanisms include gate-oxide breakdown, electromigration, stress migration, hot carrier injection degradation, etc. Data extrapolation is performed using conditions based upon reliability and failure distribution models. Reliability simulators such as BTABERT(copyright) are used to calculate circuit xe2x80x9cagexe2x80x9d or equivalent estimates of the degree of wear-out of circuits based upon device voltage and current calculations and operating duty cycle. These data are used to predict the expected life of the circuit.
The previously mentioned hot carrier injection is one of the major reliability wear-out mechanisms in VLSI circuits. Presently, hot carrier robustness of a CMOS process is evaluated by stressing individual devices at elevated voltages and extrapolating lifetime to the standard operating voltage (Vdd). As device geometries shrink, the electric field generating hot carriers is increasing dramatically. The time a device is stressed in standard operation is quite small and accordingly, the lifetime estimates using current extrapolating methods become less and less effective. Simulation efforts to model hot carrier injection in large VLSI devices can be time consuming and inaccurate. Additionally, as design cycles shorten, little time is afforded to perform these complex simulations. The iterative nature of degraded circuit simulations make these design cycles even longer and modeling hot carrier effects at all process corners and for all process variations can be quite challenging.
Therefore, there is a need for test structures that can be incorporated into any device that will degrade along with that device and flag an xe2x80x9cend-of-lifexe2x80x9d signal when degradation reaches a prescribed limit. This set of test structures, called the xe2x80x9con-chip reliability monitorxe2x80x9d, can alleviate the need for reliability modeling. They will occupy a small area and can be included as a substitute die in the prime die area, fit into scribe lines, or placed as part of the product die. Designers need only simulate each product and test structure design for functionality and may avoid the time consuming and cumbersome task of reliability simulation. Where included in the product, the on-chip reliability monitor may be used to predict an end-of-life for a device and flag the need to replace the device.
Other approaches for determining reliability factors exist. U.S. Pat. No. 5,587,665 to Jiang teaches a method where propagation delay and rise and fall times of a series of cascaded inverters are measured under conditions with and without hot carrier induced stress. U.S. Pat. No. 6,169,694 B1 to Nam et al. teaches a method and circuit for performing on-chip wafer level burn-in of DRAM devices. Specifically tested using this method are the oxide film and capacitor failure. U.S. Pat. No. 6,136,619 to Ceuninck et al. describes a circuit and method for determining electromigration induced resistance changes in conductors. A single current source is applied to both a reference and a test conductor structure placed in close proximity on the semiconductor die. The direction of current in the reference conductor structure is alternated using an h-bridge while the current in the test conductor structure flows in only one direction. By alternating the current in the reference conductor structure, the effects of electromigration are eliminated while maintaining identical current magnitudes and conditions in both structures. U.S. Pat. No. 5,625,288 to Snyder et al. describes a method and circuit for determining high frequency reliability and failure modes in test structures. These methods incorporate DC input signals to control various test functions including temperature and operating frequency.
A principal object of the present invention is to provide a method for monitoring reliability mechanisms including hot carrier effects, gate oxide time-dependent dielectric degradation (TDDB), and electromigration.
Another object of the present invention is to provide a circuit for monitoring reliability mechanisms due to hot carrier effects.
Another object of the present invention is to provide a circuit for monitoring reliability mechanisms due to gate oxide time-dependent dielectric degradation (TDDB).
Another object of the present invention is to provide a circuit for monitoring reliability mechanisms due to electromigration.
Another object of the present invention is to provide a circuit for flagging end of lifetime when one of the reliability mechanisms being monitored exceeds a predetermined threshold prior to failure of the active device, thereby reducing the downtime of the system where the device is utilized.
These objects are achieved using a system with three on chip monitoring test structures. If any of the three test structures indicates an end of life failure, a bit will be set indicating that the IC is near failure and should be replaced. This is done prior to actual device failure and will eliminate down time of the system where this IC is used.
The first test structure monitors hot carrier degradation. The circuit is comprised of two ring oscillators; one with its transistors subjected to hot carrier effects (degrading ring oscillator) and one not subjected to hot carrier effects (non-degrading ring oscillator). Initially, both ring oscillators will each have fixed frequencies. The two frequencies need not be identical. The degrading ring oscillator is applied to the input to a binary counter. The non-degrading ring oscillator frequency is divided down to a lower frequency. This divided frequency gates the binary counter on in one state and resets the counter in the other state. Just after manufacturing, the binary counter will see a finite number of counts xe2x80x9cixe2x80x9d during each gating cycle. As the degrading ring oscillator frequency drops due to hot carrier effects, the binary counter will at some point see fewer pulses applied and the resulting count will be xe2x80x9cjxe2x80x9d (where j less than i). The designer will determine the difference (ixe2x88x92j) where degradation indicates a reliability issue and the circuit will then generate an end of life signal if (ixe2x88x92j) exceeds a certain predetermined limit.
The second test structure monitors gate oxide TDDB degradation. A plurality of xe2x80x9cNxe2x80x9d parallel connected capacitors have a stress voltage applied to them such that the time to failure is some fraction of the time to failure experienced under normal use. Breakdown of a capacitor is observed by a change of resistance of the structure and is used to trigger a bit indicating a TDDB end of life signal.
The third test structure monitors electromigration degradation. xe2x80x9cMxe2x80x9d minimum width metal lines are connected in parallel. A current is applied to them such that the time to failure is some fraction of the time to failure experienced under normal use. Breakdown of a metal line is observed by a change of resistance of the structure and is used to trigger a bit indicating an electromigration end of life signal.